Integrated circuit wire and/or transistor fabrication may be important issues in research for enhancing electrical characteristics of semiconductor devices. For example, transistors may be fabricated using manufacturing processes that may be similar to that of integrated circuit wires or traces. To this end, the manufacturing process may provide transistors with gate electrodes defined in a predetermined region of a substrate. Accordingly, the transistor may have enhanced current driving capability by using a larger channel region than when a gate electrode is formed on the predetermined region of the semiconductor substrate.
However, conventional manufacturing processes may not be easily adapted to provide structures which may allow integrated circuit wires to be electrically connected to other integrated circuit wires, for example, on different levels of metallization. This is because conventional manufacturing processes may use connection holes and/or vias to electrically connect the integrated circuit wires on different levels. The connection holes may be defined by an insulating layer on the substrate. Accordingly, in order to electrically connect the integrated circuit wires to each other, the manufacturing processes may additionally employ a semiconductor deposition technique associated with the insulating layer, and semiconductor photolithography and etching techniques associated with the connection hole.
Metal wires electrically connected through connection holes in an insulating layer are disclosed in U.S. Pat. No. 5,834,369 to Tomoyasu Murakami et al. According to U.S. Pat. No. 5,834,369, a lower metal wire is formed on a substrate. An insulating layer is formed on the substrate to cover the lower metal wire. A connection hole is formed in the insulating layer to expose the lower metal wire. A tungsten plug is formed in the connection hole. An upper metal wire partially in contact with the tungsten plug is formed on the insulating layer.